Design and Implementation of Reconfigurable Microstrip Antenna

Vol. 3 No. 1

Year: 2014

Issue: Nov-Jan

Title : Design and Implementation of Reconfigurable Microstrip Antenna

Author Name : M.Alwin, P.Jothilakshmi

Synopsis :

A simple new design of Microstrip Patch Antenna has been designed to tune a set of different discrete frequencies. The frequency variation is achieved by changing the electrically actuated RF switches. The antenna’s operative condition is controlled between different states by biasing. The simulation of the designed antenna is done using Advanced design system and its observed parameters are documented in this paper.

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Analysis and Design of Hysteresis Comparator

Vol. 3 No. 1

Year: 2014

Issue: Nov-Jan

Title : Analysis and Design of Hysteresis Comparator

Author Name : M.Bharanidharan, Shenbagapariya M, Santhiyakumari N

Synopsis :

The main building block of any portable electronic equipment is the Analog-to-Digital Converter. The increased demand of the portable electronic equipments has forced the circuit designers to use lower supply voltages. However, the performance of analog circuits is degraded at low supply voltage due to large power dissipation and higher noise occurrence. This makes the design of voltage analogue circuits more challenging. As comparator is the basic device of analog to digital converters, this paper aims to analyze the comparator design with hysteresis. This proposed technique reduces the power dissipation and noise. The results were compared with the double tail comparator, which operates with supply voltage of 0.6v.

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Vehicle Speed Violation Control and Tracking using GSM

Vol. 3 No. 1

Year: 2014

Issue: Nov-Jan

Title : Vehicle Speed Violation Control and Tracking using GSM

Author Name : M.Pratheba, G.Sekhar , K.Sivaprakash

Synopsis :

Violation of traffic rules is a major problem in the current scenario. This paper mainly deals with the control of rules and regulations in the traffic. The recently developed technologies help us to solve the problem easily and wisely. In this paper, the speed of the rider is monitored. If any violation of rules in speed or rash driving is found, a fine is provided to the rider immediately through a message.

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Identification of the Flood Attackers and effective delivery of Packets in Disruption Tolerant Networks

Vol. 3 No. 1

Year: 2014

Issue: Nov-Jan

Title : Identification of the Flood Attackers and effective delivery of Packets in Disruption Tolerant Networks

Author Name : P.S.Nandhini, P.Suresh

Synopsis :

Disruption Tolerant Network (DTN) is a networking architecture that is designed to provide communications in the most unstable and stressed environment. DTN is normally be subjected to frequent disruptions. Due to restriction in network resources such as contact opportunity and buffer space, DTNs are exposed to flood attacks. Flooding is a denial of service attack that is designed to bring a network or service down by flooding it with large amount of traffic. In this paper, limiting the rate is used to be defined against flood attacks in DTNs, so that each node limits the number of packets that can be generated in each time interval and the number of replica that can be generated for each packet. It is a distributed scheme to detect the violation of rate limits. The detection scheme uses claim-carry-and-check mechanism. The structure of the claim adopts the pigeonhole principle to detect the attacker. The detection of the attacker and the efficiency of the proposed scheme are determined using the event driven simulations.

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Prioritized PWDEDF Scheduling Algorithm for QoS Enhancement using Network Processor

Vol. 3 No. 1

Year: 2014

Issue: Nov-Jan

Title : Prioritized PWDEDF Scheduling Algorithm for QoS Enhancement using Network Processor

Author Name : Anna sudha

Synopsis :

The main objective of this paper is to implement the Prioritized Weighted Deficit Earliest Departure First (PWDEDF) scheduling algorithm in a Network Processor (NP) based on router to enhance the multimedia applications. The performance is measured using Network Processor Simulator. The effectiveness of PWDEDF algorithm has been verified by simulations using Intel IXP 2400 NP. Network Processors are emerging as a very promising platform due to their capability of combining the flexibility of General-purpose processors with the high performance of hardware-based solutions. The results shows that, PWDEDF achieves reduction in jitter compared to EDF for different traffic type. Also PWDEDF has 97% less delay compared to EDF (Earliest Deadline First) scheduling algorithm for real time flows.

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