Design and Implementation of Cache Memory with FIFO Cache-Control

Volume 7 Issue 1 November - January 2018

Research Paper

Design and Implementation of Cache Memory with FIFO Cache-Control

Anamika Upadhyay*, Vinay Sahu**, Sumit Kumar Roy***, Dharmendra Singh****

*-** UG Scholar, Department of Electronics and Telecommunication, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Raipur, Bhilai, India.

***-**** Assistant Professor, Department of Electronics and Telecommunication Engineering, Shri Shankaracharya Institute of Professional Management and Technology (SSIPMT), Raipur, Bhilai, India.

Upadhyay, A., Sahu, V., Roy, S. K., Singh, D. (2018). Design and Implementation of Cache Memory with FIFO Cache-Control. i-manager’s Journal on Communication Engineering and Systems, 7(1), 16-21. https://doi.org/10.26634/jcs.7.1.13959

Abstract

In today's world, the multi-core processor is very popular and has huge applications in Digital Signal Processing, Networking, Embedded System, General Purpose Computers etc. As the single-core processor has its own limitations, and complexities because of a single core, a multi-core processor attracts many researchers to work for the improvements in time and power consumption of the system, as it contains multi independent central processing units. The cache coherence is one of the major issues of the multi-core processor and cache handling is more complicated. Hence, it is important to design a method, so that the cache memory can be handled. In this paper, authors have proposed a design to utilize the cache memory in an efficient manner in the supervision of cache controller and also for reducing the power consumption.